Hi All,
Here's a short status update:
- We found a PCB-bug on the planned OpenRISC-ASIC FPGA development board, which has now been corrected and the board will be assembled during end of next week. We managed to test some of the functionalities on the old "incorrect" board, so hopefully the board-bring-up will go faster this second time.
We have also started to create a SoC design for this board, that we can use as a base-design to validate some of the features that we want to include in the final OpenRISC ASIC design (TBD).

We will get back with more information as soon as we have received the new FPGA dev-boards, so cross your fingers :-) and have a nice weekend.

Cheers,
Marcus Erlandsson, ORSoC.se

Just thought I'd mention that I wrote and submitted an article about OpenRISC for Linux Journal since OpenRISC support is now included in the 3.1 kernel. It is mostly a general overview of how to get started from a Linux software developers perspective. The publication date will be after February 6th next year if it is accepted for publication so you may have a sudden influx of Linux developers interested in purchasing a board around then. ;-)

James

That is great!!!!!
This is exactly what we need to do, meaning that we all need to "help out" and spread the world about what we are trying to do -> "creating the world first community owned OpenRISC processor ASIC".

We plan to put allot of effort into making sure that it will be "super easy" to get started with this new board, so that we can get all kind of engineers involved in this project helping out verifying the design, and to get feedback on what function/features that should be included in the final ASIC version.

The board are being assembled on Friday.......can't wait start testing the first samples...

/Marcus

What is "OpenRISC-ASIC FPGA development board" ? Have you a link to it ? OpenRisc will be embedded in which FPGA ?

Short status update on the new OpenRISC development boards:
The board was delayed by the production/assembly company, but we finally received the first prototypes last Friday. We have now started to test these and so far all looks good, meaning no fire or smoke :-)
We have now started to test the main peripheral interfaces, more updates will arrive later this week.

/Marcus at ORSoC.se

FPGA dev-board testing update:
We have now got the OpenRISC processor, uart, sdram, ethernet, spi-flash up and running. The next functions to test is usb, sd-card-controller.

/Marcus at ORSoC.se

Hi OpenRISC-ASIC supporters,
As you might have seen on the OpenRISC-forum, we have now released the new OpenRISC FPGA development board. Our suggestion now is that we use this board to design and verify the OpenRISC-ASIC design. You can read more about the board here:

http://opencores.org/or1k/Ordb2a-ep4ce22


We have also developed a OpenRISC-SoC design that is almost using all of the peripherals, which we can use as a base-design to start with, and then together modify/remove/add functions so that we make sure that all OpenRISC-ASIC functions are implemented and tested using this board.
Since we have two optional connectors with GPIO-signals on this board, we can fairly easy add additional peripherals by developing a daughter-board when we have defined these peripherals.

So we hope that this new FPGA-development boards will trigger the following actions:

1. Get the current OpenRISC-supporters more engaged into the project, by helping out with both development and verification. The board are available at self-cost in OpenCores webshop (http://opencores.org/shop,item,9)

2. Show the rest of the open-source community that we are on our way towards our goal, making the worlds first community ASIC, and that this hopefully will trigger more people to help out with donation and the development/verification workload.


We would also like to invite more commercial companies into this project, since they could benefit allot of getting a processor ASIC that is open-source, which will give them benefits like:
- "End of life" security: since the whole design is open-source it's easy to port this SoC-design into another ASIC or FPGA when/if the OpenRISC-ASIC becomes obsolete.
- Technology-independent
- License fee free


So let's try and take this project to the next stage.........

So how does this sound, feedback is very appreciated?!


/Marcus at ORSoC.se

Hi guys,
It looks great. Congratulations.
If I may propose a possible extension board in the future then I vote for CAN (+ CANOpen).
Thanks for all the effort.
Regards,
baltazar

Hi guys,
It looks great. Congratulations.
If I may propose a possible extension board in the future then I vote for CAN (+ CANOpen).
Thanks for all the effort.
Regards,
baltazar

Hi,
a CAN extension board would also be ontop of my list.
vote +1

Br,
Bertil

The article that James has been writing is available now. It's a really good article, and very nice to see an ASIC layout of OpenRISC too. Congratulations to the publication. Here's the link http://www.linuxjournaldigital.com/linuxjournal/201112/?pg=102#pg99

It does run faster than 50MHz in FPGA though ;)

--
Olof Kindgren
______________________________________________
ORSoC
Website: www.orsoc.se
Email: olof.kindgren@orsoc.se
______________________________________________
FPGA, ASIC, DSP - embedded SoC design

Well done!

Thank you for posting the update; deadlines have kept me from mentioning it here. Apparently, acceptance of the OpenRISC kernel patch into the main kernel development line caused interest to heat up so Linux Journal bumped the article to the front of the publication schedule.



Heheheh, I wish I had time to verify that. :) How fast have you made it run? Which FPGA(s) did you use? I'm curious to try it out on the new FPGAs from Achronix (www.achronix.com). Apparently they can run at 1.5GHz and have DDR3 controller cores built in.

James

Yes, we are also very interested in making ports for FPGAs from Archonix, Tabula and SiliconBlue (soon to be Lattice). The main problems are availability of dev tools, boards and hours in the day. Hopefully someone with access to those things can post some results here

Regarding the speed, we have the ML501 port running at 66MHz. You can keep an eye on this page (http://opencores.org/or1k/FPGA_Development_Boards) to see current status of the different boards supported in ORPSoC

We also have more theoretical numbers, thanks to a collaboration with Plunify. You can find implementation statistics for a broad range of FPGAs here http://opencores.org/openrisc,plunify I think one of the large Virtex-5 FPGAs has the highest score there. Note that this is for the or1200 RTL only, without any peripherals included. It could still serve as an indicator though

Thanks again for a great article. Hope to see more of those in the future

Best Regards,
--
Olof Kindgren
______________________________________________
ORSoC
Website: www.orsoc.se
Email: olof.kindgren@orsoc.se
______________________________________________
FPGA, ASIC, DSP - embedded SoC design

I have some questions about the evolution of the project.

Are there any public mailing lists about the development, or is the team closed and the designs internal? I don't know in which part of the site I should be looking, but I didn't see any information about the design of the FPGA boards practically until they were already available for sale. Are the gerber/schematic files of the FPGA boards open? I was hoping there could be some participation from the open hardware community besides funding.